##MIPS Processor in Verilog##
Building a simple pipelined processor in Verilog (ugh) with data forwarding and branch prediction.
Couldn't get it to synthesize unfortunately :( (why do we use Verilog for this stuff???)
Processor repo
##MIPS Processor in Verilog##
Building a simple pipelined processor in Verilog (ugh) with data forwarding and branch prediction.
Couldn't get it to synthesize unfortunately :( (why do we use Verilog for this stuff???)
Processor repo