CHN-ChenYi / Tetris-on-SWORD-LCDF2021

Tetris in Verilog -- a course project for Logic and Computer Design Fundamentals Course at ZJU.

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Tetris-on-SWORD

Tetris in Verilog -- a course project for Logic and Computer Design Fundamentals Course at ZJU.

Interface

scoreCount

scoreCount sC1(.clk(clk),.rst(rst),hit(hit),.lineCount(lineCount),.SEGCLK(SEGCLK),.(SEGCLR),.SEGDT(SEGDT),.SEGEN(SEGEN));
  • rst reset button, 1 for reset
  • clk clock
  • hit 1 for user have at least 1 line cleared
  • lineCount
    • 00 for clear 1 line
    • 01 for clear 2 lines
    • 10 for clear 3 lines
    • 11 for clear 4 lines
  • SEGCLK SEGCLR SEGDT SEGEN for display

keyboard

pattern

190 191 192 193 194 195 196 197 198 199
180 181 182 183 184 185 186 187 188 189
170 171 172 173 174 175 176 177 178 179
160 161 162 163 164 165 166 167 168 169
150 151 152 153 154 155 156 157 158 159
140 141 142 143 144 145 146 147 148 149
130 131 132 133 134 135 136 137 138 139
120 121 122 123 124 125 126 127 128 129
110 111 112 113 114 115 116 117 118 119
100 101 102 103 104 105 106 107 108 109
90  91  92  93  94  95  96  97  98  99
80  81  82  83  84  85  86  87  88  89
70  71  72  73  74  75  76  77  78  79
60  61  62  63  64  65  66  67  68  69
50  51  52  53  54  55  56  57  58  59
40  41  42  43  44  45  46  47  48  49
30  31  32  33  34  35  36  37  38  39
20  21  22  23  24  25  26  27  28  29
10  11  12  13  14  15  16  17  18  19 
0   1   2   3   4   5   6   7   8   9   

pattern 1

Empty.

static[0:199] = 200'b0;

pattern 2

Last row to be eliminated.

static[0:9] = 10'b1111111111;
static[10:19] = 10'b1110000011;
static[20:29] = 10'b1000000011;
static[30:199] = 170'b0;

pattern 3

After pattern 2 is eliminated.

static[0:9] = 10'b1111111111;
static[10:19] = 10'b1110000011;
static[20:29] = 10'b1000000011;
static[30:199] = 170'b0;

pattern 4

Two continuous rows to be eliminated.

static[0:9] = 10'b1111111111;
static[10:19] = 10'b1111111111;
static[20:29] = 10'b1110000011;
static[30:39] = 10'b1000000011;
static[40:199] = 170'b0;

About

Tetris in Verilog -- a course project for Logic and Computer Design Fundamentals Course at ZJU.


Languages

Language:Verilog 35.2%Language:VHDL 25.5%Language:Tcl 19.3%Language:Shell 8.6%Language:HTML 3.9%Language:Stata 3.7%Language:Batchfile 3.3%Language:SystemVerilog 0.5%