Bochen Ye's repositories
Tiny_LeViT_Hardware_Accelerator
This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.
MNIST-handwritten-digit-classification
This is a lab of python in deep learning. we want to generate a multilayer perceptron for handwritten digit classification from scratch: Using only NumPy and matplotlib libraries.
OpenSoCFabric
OpenSoC Fabric - A Network-On-Chip Generator
Network-on-Chip-Router-Based-on-Packet-Connected-Circuit
This is my bachelor graduation project. It's a Network on Chip using by Verilog HDL. This 2D-Mesh NoC based on packet connected circuit.
RISC-V-five-stage-CPU
This is a project base on book 'Digital design and computer architure RISC-V edition'. I use Verilog to build RISC-V CPU.
SpkingNN-on-Chip
This is a collection of papers I read on SNN accelerators.
5SIB0_EDA_Quine-McCluskey_algorithm
This is our report and code of 5SIB0 in TU/e, 2023. It is about validate QM algorithm by using Python.
Awesome-PyTorch-Chinese
【干货】史上最全的PyTorch学习资源汇总
Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functi
BoChen-Ye.github.io
AcadHomepage: A Modern and Responsive Academic Personal Homepage
BoChen-Ye
About Config files for my GitHub profile.
chisel-tutorial
chisel tutorial exercises and answers
CNN-accelerator
CNN accelerator
CudaSteps
基于《cuda编程-基础与实践》（樊哲勇 著）的cuda学习之路。
deeplearning-models
A collection of various deep learning architectures, models, and tips
Digital-IC
数字IC相关资料
Digital_IC_Project_Verilog-SystemVerilog
This is a repo of practicing digital IC by using Verilog HDL and SystemVerilog.
HDLBits_Solution
My solution to the problem set on HDLBits.
hw
RTL, Cmodel, and testbench for NVDLA
mips-cpu
MIPS CPU implemented in Verilog
NyuziGPU
GPGPU microprocessor architecture
Perl_intro
:dromedary_camel: Introductory course for Perl 5 through examples, geared towards VLSI engineers
RISC-V-CPU
RISC V core implementation using Verilog.
tensil
Open source machine learning accelerators
tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
tue-deeplearning-2021
Repository for Tutorials and Practicals part of the Deep Learning course at TU/e