Dhinesh's repositories
Accelerating_Standard_and_Modified_AES128
Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
Accelerating-Mandelbrot-Fractal-on-FPGA
Hardware acceleration of mandelbrot fractal generation on PYNQ-Z1 FPGA as part of EE5332 IIT Madras course project
Digital-Design-on-FPGA--Phaseshift22
This course will be an in-depth hands-on demo session on the Virtual FPGA Lab using the open-source Makerchip IDE Web platform.
Bitonic-Sorting-In-Verilog
Bitonic Sorting in Verilog which sorts any number of elements which are a power of two
GettingStartedWithFPGAs
Content for the FPGA Primer Course offered by the OSFPGA Foundation, Redwood EDA, and VLSI System Design.
riscv-bitmanip
RISC-V Bit Manipulation extension, CAD for VLSI(CS6230) Course project, IIT Madras
al-folio
A beautiful, simple, clean, and responsive Jekyll theme for academics
baladhinesh.github.io
Personal website
circuit-solver.github.io
This is Circuit Solver which can solve any kind of circuit for you. Do check it out!!
EE06_Projtask1
Project draft on how to implement keyboard and touchpad on a single hardware and toggling between them
elec_coord_self_project
Electronics Club Self Project for Coordinators
Electronics-Club-MS-Website
This is a website for Mega Session 2022 conducted by Electronics Club, CFI.
FPGA-Remote-Lab-Setup
This project FPGA Remote Lab Setup is part of mini-project guided by Prof. Nitin Chandarchoodan, EE IITM
risc-v-myth-workshop-august-mukuljava
risc-v-myth-workshop-august-mukuljava created by GitHub Classroom
RISC-V_MYTH_Workshop
Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
ultra-maple-42121
Personal portfolio website. Repo is WORK IN PROGRESS
Web-Development
Some basic projects