Generator of synthesizable float point operators in Verilog HDL
Depends:
Format constraints:
- Little endian.
- sign-expt_msb==1
- expt_lsb-frac_msb==1
- frac_lsb==0
Operators:
Generator of synthesizable float point operators in Verilog HDL
Generator of synthesizable float point operators in Verilog HDL
Depends:
Format constraints:
Operators:
Generator of synthesizable float point operators in Verilog HDL
BSD 3-Clause "New" or "Revised" License