Ashwin-Rajesh / riscv

A RISC V processor with memory hierarchy with separate instruction and data cache (tested on FPGA with GCC compiled code)

RISCV Processor Design

This project was done as part of the processor system design course by Prof. Kuruvila Varghese at the Department of Electronic Systems Engineering at the Indian Institute of Science, Bangalore.

Code

The RTL subfolder has the code for the different blocks in the system implemented on the FPGA

Reports

Cache subsystem design report

Pipeliend processor core design report

Multicycle processor design report