ArvinDelavari

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Iran University of Science and Technology

Tehran

Organizations

IUST-Computer-Organization

phoeniX-Digital-Design

Arvin Delavari's starred repositories

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language:SystemVerilogNOASSERTION13600

oh

Verilog library for ASIC and FPGA designers

Language:VerilogMIT111500

bringup-bench

Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, accelerators, compilers and operating systems. You probably don't need Bringup-Bench, but if you do, you probably need it badly!

Language:CNOASSERTION10500

phoeniX

phoeniX RISC-V Processor

Language:VerilogGPL-3.09000

tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Language:SystemVerilog641200

OpenRAM

An open-source static random access memory (SRAM) compiler.

Language:PythonBSD-3-Clause76300

riscv-coremark

Setup scripts and files needed to compile CoreMark on RISC-V

Language:CBSD-3-Clause5300

pulp_cluster

The multi-core cluster of a PULP system.

Language:SystemVerilogNOASSERTION4200

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language:SystemVerilogNOASSERTION96000

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Language:SystemVerilogApache-2.038300

riscv-dv

Random instruction generator for RISC-V processor verification

Language:PythonApache-2.096300

biriscv

32-bit Superscalar RISC-V CPU

Language:VerilogApache-2.078700

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

Language:CApache-2.024000

xv6-riscv

Xv6 for RISC-V

Language:CNOASSERTION638500

sv2v

SystemVerilog to Verilog conversion

Language:HaskellBSD-3-Clause48900

iob-cache

Verilog Configurable Cache

Language:VerilogMIT14800

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

Language:SystemVerilogApache-2.092900

x-heep

eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V

Language:CNOASSERTION12700

linear-control-systems-project

Design of a lead-lag controller

700

common_cells

Common SystemVerilog components

Language:SystemVerilogNOASSERTION45800

Vitis_Libraries

Vitis Libraries

Language:C++Apache-2.083200

Vitis-Tutorials

Vitis In-Depth Tutorials

Language:CMIT110900

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Language:SystemVerilogNOASSERTION89100

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Language:AssemblyNOASSERTION212100

iob-soc

RISC-V System on Chip Template

Language:VerilogMIT14500

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Language:VerilogBSD-3-Clause138900

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

Language:CNOASSERTION323900

linux

Linux kernel source tree

Language:CNOASSERTION4800

AssembleX

RISC-V Assembly Software Assistant

Language:PythonGPL-3.0500

linux-xlnx

The official Linux kernel from Xilinx

Language:CNOASSERTION129800