he-soc
1.0 Setting up the project
-
Clone this repository.
-
Update the
setup.sh
to point to your toolchain installation paths. -
Run the following comamnds inside
he-soc
.git clone https://github.com/AlSaqr-platform/cva6.git git submodule update --init --recursive
To compile the code:
source setup.sh cd software/hello make clean all
-
Before building the RTL using Bender, copy the contents of the vip folder (you can find this folder in the original he-soc repo in the VM) to the following path:
he-soc/hardware/tb/vip
. -
Build the RTL by running the following commands. Make sure, for simulation, to add the
localjtag=1
andpreload=1
flag to themake scripts_vip
command.make update make scripts_vip
-
Compile the code.
cd ../software/hello/ make clean all
-
Running simulation
-
Go into the CVA6 folder at
he-soc/cva6
and run the following commands:git submodule update --init --recursive
-
Install Verilator Simulation Flow (this is from CVA6)
- Setup install directory RISCV environment variable i.e. export
RISCV=/YOUR/TOOLCHAIN/INSTALLATION/DIRECTORY
. - Run
./ci/setup.sh
to install all required tools (i.e. verilator, device-tree-compiler, riscv64-unknown-elf-*, ..)
- Setup install directory RISCV environment variable i.e. export
You can install verilator from source using
./ci/install-verilator.sh
or by manually installingverilator >= 4.002
Note: There is currently a known issue with version 4.106 and 4.108. 4.106 does not compile and 4.108 hangs after a couple of cycles simulation time.)- Build model and simulation
- Build the Verilator model of CVA6 by using the Makefile:
make verilate make build
- Copy the
work-dpi
folder that is created in the main folder of the CVA6 repo tohe-soc/hardware
- Build the Verilator model of CVA6 by using the Makefile:
Now, you can run the simulation.
Debugging
-
Error
Failed to open design unit file "./he-soc/hardware/tb/vip/hyperflash_model/s26ks512s.v" in read mode.
Make sure you have imported the verification IPs (VIPs) to the correct location (Step 4).
-
-
Testing on the board
To generate the bitstream go to the
hardware
folder and run the following commands:bender update make simple-padframe=1 scripts-bender-fpga-ddr exclude-cluster=1
Then enter
fpga
folder and runsource setup.sh
.The settings you need to use for
source setup.sh
are:- VCU 118,
- Yes, instantiate the LLC,
- DDR4,
- Yes, validate the peripherals.
Once done, you need to run the following:
make ips make clean run
Debugging
-
Error It is possible that you get an error:
vivado-2018.2 not found. No such command.
Fix:
- Go to the
Makefile
in./alsaqr/tcl/ips/*
. There are multiple ips here: boot_rom, clk_mngr, etc. and you need to do this for all of them. - Update the
vivado-2018.2 vivado
command in both rulesall
andgui
with the command that works for your system. If you are using the VM, then should replacevivado-2018.2 vivado -mode batch -source run.tcl
withvivado -mode batch -source run.tcl
(and the same for thegui
rule).
- Go to the
-
Error When you run
make clean all
and get an error forIP not found
in the Vivado GUI.Fix:
-
gdb
Commands- Connect to a new target:
target remote:3333
ORtarget extended-remote:3333
. - To mask the SIGINT signal:
handle signal SIGINT noprint
, it works only withextended-remote
.
- Connect to a new target: