Anjali Jaiswal's repositories
SPI-Interface
UVM Testbench to verify serial transmission of data between SPI master and slave
Synchronous-FIFO-UVM-TB
UVM Testbench for synchronus fifo
Sequence-Detector-using-FSM
RTL for sequence detector in verilog
UVM Testbench to verify serial transmission of data between SPI master and slave
UVM Testbench for synchronus fifo
RTL for sequence detector in verilog