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AlisonNi / DDR2_memory_interface

A DDR2 memory interface for the Digilent Nexys4 board that does not rely on the Xilinx MIG

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DDR2_memory_interface

A DDR2 memory interface for the Digilent Nexys4 board that does not rely on the Xilinx MIG. This project is based on a working DDR2 interface very kindly donated by a friend. Please note that this is currently an unfinished implementation with a number of serious limitations.

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A DDR2 memory interface for the Digilent Nexys4 board that does not rely on the Xilinx MIG

License:GNU General Public License v2.0

Languages

Language:Verilog 53.0%Language:VHDL 32.8%Language:SystemVerilog 13.9%Language:Tcl 0.3%