This project was realized as final test for the Digital Logic Design (Italian equivalent: Reti Logiche) course as part of my Bachelor's Degree in Politecnico di Milano.
The VHDL program is required to implement a convolutional algorithm. The hardware module has to serialize a flow of 8-bit words and then apply a convolutional algorithm with transmission rate 1/2 on it, producing a continuous stream of bits. See *project_task.pdf" for details.