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AlexLee1999 / Single-Cycle-RISCV-CPU

A Single Cycle RISCV written in Verilog

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Single-Cycle-RISCV-CPU

Supported Operation

ADD SUB SLTI SLLI SRLI SRAI OR AND XOR MUL

About

A Single Cycle RISCV written in Verilog

Languages

Language:Verilog 88.2%Language:Python 6.0%Language:Assembly 5.8%