Akh07 (AkhilHadli7)

AkhilHadli7

Geek Repo

Company:Textron

Location:India

Home Page:https://osvlsi.blogspot.com/

Github PK Tool:Github PK Tool

Akh07's starred repositories

Accelerating-CNN-with-FPGA

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

Language:C++License:NOASSERTIONStargazers:736Issues:0Issues:0

CNN_hardware_accelerator

project in course related to VLSI-CAD

Language:VerilogStargazers:3Issues:0Issues:0

Computer_Architecture_Course_Projects

🎓💻University of Tehran Computer Architecture Course Projects - Spring 2021

Language:VerilogStargazers:2Issues:0Issues:0

CNN-pruning

Prunning a deep learning model of COVID19 detection

Language:Jupyter NotebookLicense:UnlicenseStargazers:1Issues:0Issues:0

cnn-accelerator

A Convolutional Neural Network (CNN) hardware accelerator for image recognition

Language:C++Stargazers:10Issues:0Issues:0

Standard-Cell-Characterization

Open Source tool to build liberty files and for Characterizing Standard Cells.

Language:PythonStargazers:24Issues:0Issues:0
Stargazers:1Issues:0Issues:0

CNN_VGG19_verilog

Convolution Neural Network of vgg19 model in verilog

Language:VerilogStargazers:45Issues:0Issues:0
Language:VHDLStargazers:5Issues:0Issues:0

shell-scripting-for-beginners-course

Notes from Shell Scripting for Beginners course

Stargazers:543Issues:0Issues:0

CNN-Accelerator

Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.

Language:VerilogStargazers:20Issues:0Issues:0

cnn_open

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

Language:CoqStargazers:217Issues:0Issues:0

Convolutional-Neural-Network

Implementation of CNN using Verilog

Language:VerilogStargazers:194Issues:0Issues:0

Coursera-VLSI-CAD

My personal collection of MOOC VLSI-CAD on coursera. It mainly consists of my solutions to programming projects in it and also some notebooks.

Language:PythonStargazers:1Issues:0Issues:0

snn-networking

Neuromorphic computing is a new technology which uses very-large-scale integration (VLSI) systems containing electrical analogs that mimic neurobiological structures. Such technology can be simulated using the Python framework snnTorch, a derivative of the deep learning framework PyTorch that has the capacity to run spiking neural networks (SNNs) which in turn can be run on neuromorphic chips. This project serves to explore the use of the snnTorch framework on a networking dataset from the Barcelona Neural Networking Center. Not only are the performance results and construction of a spiking neural network seen from this experiment, but also important characteristics of types of data that can be collected that will better fit the spatio-temporal data characteristics that are ideal to be run in an SNN. Moreover, cloud computing tools from Amazon Web Service (AWS) such as S3 and SageMaker were used to aid in the completion of running deep learning experiments. This work serves as an artificial intelligence proof of concept for the snnTorch framework and cloud computing in the deep learning environment.

Language:PythonStargazers:9Issues:0Issues:0

TechSeminar_IndustrialTrain_Reports

Repository Containing Approved Reports of Technical Seminar and Industrial Training Reports for 7th SEM CSE- Siddaganga Institute of Technology

Stargazers:1Issues:0Issues:0

dvi2vga_lap

The 1280x720 60P image of input from the HDMI input of ZYBO in real time and then output to the VGA terminal by Laplacian filter processing.This is a project of Vivado 2015.2.

Language:VHDLStargazers:2Issues:0Issues:0

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

Language:PythonLicense:MITStargazers:1940Issues:0Issues:0

RTL-PowerOptimization

Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

Language:VerilogLicense:BSD-3-ClauseStargazers:11Issues:0Issues:0

DLX-Microprocessor

Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.

Language:VerilogLicense:BSD-2-ClauseStargazers:8Issues:0Issues:0

quartus_test

a simple altera intel quartus design with tcl script

Language:TclStargazers:2Issues:0Issues:0
Language:PythonStargazers:72Issues:0Issues:0

Deep-Neural-Network-Hardware-Accelerator

SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software

Language:SystemVerilogStargazers:98Issues:0Issues:0

Image-Classification-using-CNN-on-FPGA

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

Language:VerilogStargazers:126Issues:0Issues:0

bfcpu2

A pipelined brainfuck softcore in Verilog

Language:VerilogLicense:MITStargazers:17Issues:0Issues:0

scripts

Automation scripts for RTL design

Language:PerlStargazers:3Issues:0Issues:0

verilog_ips

Various IPs implemented in Verilog

Language:SystemVerilogLicense:ISCStargazers:7Issues:0Issues:0

Physical-Design-of-ASICs

TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.

Language:TclStargazers:11Issues:0Issues:0