VirtualLogicLabs
Rutgers University - Spring 2018 - Electrical and Computer Engineering, Software Engineering Group 10 Project. The purpose of this repository is to present an organized folder for the demo presentation and requirements. The actual development repository is at the linked repository. https://github.com/SagarPhanda/VirtualLogicLabs
The following are the project's authors: Khalid Akash, Yiwen Tao, Vikas Khan, Sagar Phanda, Joe Cella, Dhruvik Patel
Instructions on testing/using the program. Navigate to the 1_code/VirtualLogicLab/ directory and execute the VLLDemo.exe file. A hardcoded login can be used to try the program: Username = student, Password = student.