AUCOHL / Lighter

An automatic clock gating utility

AUCOHL/Lighter Issues

Update Reports to include $SDFFE cells
Closed a year ago
Fix all platforms' map files
Updated a year ago
SDFFE mapping crashes validation
Closed a year ago2
Add liberty file for GF180 PDK
Closed a year ago2
can i try this in openlane's yosys.
Closed a year ago9
Incorporate Lighter into OpenLane.
Updated a year ago
Move module to be part of yosys-f4pga-plugins
Closed a year ago5
Add support for other open source PDKs.
Updated 2 years ago2
Make the plugin selection for both techmap and memory commands
Closed 2 years ago1
Power report does not consider clock-gating cells high activity
Closed 2 years ago4
Make lighter PDK independent
Closed 2 years ago1
report_power.py needs to be generic
Closed 2 years ago1
Move power_report_summary.csv from the root to a subfolder
Closed 2 years ago1
Add support for other sky130 standard cell libraries.
Closed 2 years ago1
Blake2s_core clock gated design fails in validation
Closed 2 years ago1