Beast code in Giters

ARmirKhan's starred repositories

ZenlessZoneZero-Auto

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SpinalHDL

Scala based HDL

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Jailbreak

iOS 17 - iOS 17.5.1 Jailbreak Tools, Cydia/Sileo/Zebra Tweaks & Jailbreak Related News Updates || AI Jailbreak Finder 👇👇

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Shadowrocket-ADBlock-Rules

提供多款 Shadowrocket 规则，带广告过滤功能。用于 iOS 未越狱设备选择性地自动翻墙。

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tvip-axi

AMBA AXI VIP

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AMBA_AXI3

System Verilog and Emulation. Written all the five channels.

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AXI4_LiteIP

A verilog FPGA Interface for AXI4_Lite from Slave side

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ARM_AMBA_Design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

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AMBA_AXI_AHB_APB

AMBA bus lecture material

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AMBA-AXI4-Lite

Master and Slave made using AMBA AXI4 Lite protocol.

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Verilog-caches

Various caches written in Verilog-HDL

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PseudoLRUCache

A parametrizable N-way associative cache memory that uses the clock algorithm to approximate a least recently used replacement policy.

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basic_verilog

Must-have verilog systemverilog modules

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async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

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darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

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axi-uvm

yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/

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uvm_axi

uvm AXI BFM(bus functional model)

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riscv-dv

Random instruction generator for RISC-V processor verification

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uvm_vim_extras

These files are intended for VIM version 7.3 or later and need to be be installed.

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zhangyouxin.github.io

personal blog

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Python-100-Days

Python - 100天从新手到大师

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i3c-slave-design

MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.

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mips-cpu

MIPS CPU implemented in Verilog

Language:VerilogGPL-3.056100