A7med3id10

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC

learn-fpga

Learning FPGA, yosys, nextpnr, and RISC-V

Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

verilog-ethernet

Verilog Ethernet components for FPGA implementation

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

hw

RTL, Cmodel, and testbench for NVDLA

Vitis-Tutorials

Vitis In-Depth Tutorials

riscv-dv

Random instruction generator for RISC-V processor verification

coremark

CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).

chisel-book

Digital Design with Chisel

6502Emulator

Learning how a CPU works by emulating one

cvfpu

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

axiom

Axiom is a free, open source computer algebra system

LF-Building-a-RISC-V-CPU-Core

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

lingua-franca

Intuitive concurrent programming in any language

noxim

Network on Chip Simulator

AtomBusMon

This project is an open-source In-Circuit Emulator for the 6502, 65C02, Z80, 6809 and 6809E 8-bit processors. See:

trng

True Random Number Generator core implemented in Verilog.

TL-V_Projects

An overview of TL-Verilog resources and projects

UETRV-PCore

Linux Capable 32-bit RISC-V based SoC in System Verilog

chiphack

Repository and Wiki for Chip Hack events.

AMC

AMC: Asynchronous Memory Compiler

Static-Timing-Analysis-Full-Course

Static Timing Analysis Full Course

Delta-Sigma-DAC-Verilog

Delta Sigma DAC FPGA

gds2gcode

VLSI-Design-Digital-System

This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

bfu_dif_fft_rtl

The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor

Procedural-and-OOPs-with-SystemVerilog

verilog_codes