64 / eepyu

4-stage pipelined RISC-V CPU, written in SpinalHDL.

eepyu

eepyu (pronounced ee-pee-you) is a 4-stage pipelined CPU implementing the RISC-V base integer instruction set, implemented with SpinalHDL.

It is optimised for area and just about fits on a ice40 HX1K FPGA (1280 LCs) running at 40-50 MHz.

TODO

• RVFI RISC-V formal verification
• doit clean
• konata pipeline output
• optimise decoder signals