4mod3 / simple-cache-sim

A very very very very very simple cache simulator

Simple Cache-Coherence Simulator

4 Cores, each with a single L1Cache which is 64 Bytes Cache-Line and fully connected.

Cache-Block Status List

• Modified
• Shared
• Invalid

Input

traceX.txt, indicating CPU-X's L/S ops.

Usage

make build run
make clean

Lisence

MIT