3i-hust-fpga

fpga-dcn-kws

FPGA Implementation of the proposed model in master thesis.

hls4ml

Machine learning in FPGAs using HLS

vivado-hls-broadcast-optimization

[DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency

DeepLearningOnFpga

Tiny_YOLO_v3_ZYNQ

Implement Tiny YOLO v3 on ZYNQ

netscope

Neural network visualizer

LSTM-PYNQ

PAAS_V1.0

PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems

Yolov2-FPGA-CNN-

Light-HLS

Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation.

rosetta

Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs

C-LSTM

CLINK

Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.

HLS_BLSTM

The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))

Zynq_HLS_DDR_Dataflow_kernel_2mm

This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print the result via UART and check the result by comparing the data with the one from CPU compuation

RFNoC-HLS-NeuralNet

Open-Source-IPs-1

Open-Source-IPs

zynqnet

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network"