20Mhz

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

leon3mp_yosys

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

sky130_adders

Study on Adders

Sonar-on-Chip

The project is oriented to implement a multichannel signal path for ultrasonic air-coupled sonar based on MEMS wideband digital microphones

SSCS-SoC

The documentation folder for the project Sonar On Chip being part of the SSCS IEEE Circuits and Systems 2021

WiShield_user_contrib

WiShield library with user contributed features

3LFCC_AC3E

SSCS Chipathon 2022 project - DC-DC converter for space - AC3E/Valparaiso/Chile

ArduinoCore-samd

avr_examples

copperv

RISCV core

copperv2

RISCV Core

cppSaif

cpp parser for SAIF file

ee214a

EE214A Course Project

ee271

gm_id_gf180mcu

This repo contains introduction of gm/id method and its application to some OTA design examples

groove-dl

A Grooveshark song downloader in Python

issues

Liberty

Spirit X3 Liberty Format Parser. opensourceliberty.org for more info.

libertyParser

Mirror of Synopsys's Liberty parser library

saleae_qspi

sdmmc-analyzer

SD/MMC Analyzer for Saleae Logic

spice_decks

Useful spice decks

verilog-vcd-parser

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

wavehc

Automatically exported from code.google.com/p/wavehc