10xEngineers

Infinite-ISP

A camera ISP (image signal processor) pipeline that contains modules with simple to complex algorithms implemented at the application level.

Infinite-ISP_TuningTool

Infinite-ISP Tuning Tool is a console-based ISP (image signal processor) tuning application that is specifically designed to tune various modules in the Infinite-ISP_GM.

Infinite-ISP_ReferenceModel

A Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Infinite-ISP_FPGABinaries

Infinite-ISP Image Signal Processing Pipeline FPGA Binaries for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit.

riscv-ci-partners

RISC-V CI Partners Project

Infinite-ISP_Firmware

Infinite-ISP Image Signal Processing Pipeline Firmware for XCK26 Zynq® UltraScale+™ MPSoC present on Xilinx® Kria™ KV260 Vision AI Starter Kit (coming soon).

LLDB

The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.

Cloud-V-git-automation

Odoo module for integration of Cloud-V GitHub app with user repositories

core-v-verif

Functional verification project for the CORE-V family of RISC-V cores.

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

llama.cpp

Port of Facebook's LLaMA model in C/C++

10xcelerator

ahb3lite_memory

Multi-Technology RAM with AHB3Lite interface

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

aws-fpga

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

Cloud-V-ci-hifive-unleashed

This repository triggers the job build which runs on hifive unleashed

corev-llvm-project

cva6-1

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cva6-pulp

This is the fork of CVA6 intended for PULP development.

cva6_Linux_Boot

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

cvw

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.

programs

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

riscv-arch-test

riscv-ctg

riscv-ctg-1

riscv-ctg-alitariq

Fork is created for Compliance PRs

riscv-iommu

IOMMU IP compliant with the RISC-V IOMMU Specification v1.0

riscv-isa-sim-ksco

Spike, a RISC-V ISA Simulator

sail-riscv

Sail RISC-V model