Artin Isagholian (0xArt)

0xArt

Geek Repo

Location:Los Angeles

Home Page:www.circuitden.com

Github PK Tool:Github PK Tool

Artin Isagholian's repositories

Tiny_But_Mighty_I2C_Master_Verilog

I2C Master Verilog module

Language:SystemVerilogLicense:GPL-3.0Stargazers:23Issues:3Issues:2

RGMII_Ethernet_Transceiver_Verilog

Verilog module to transmit/receive to/from RGMII compatible ethernet PHY

Language:VerilogLicense:GPL-3.0Stargazers:17Issues:1Issues:1

Super_SPI_Master_Verilog

SPI Master Verilog module

Language:SystemVerilogLicense:GPL-3.0Stargazers:6Issues:2Issues:0

Passe_Passe_Network_Switch

A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.

Language:SystemVerilogLicense:MITStargazers:3Issues:1Issues:0

SuperHashProcessor

Quartus Prime project directory of a SHA1, SHA256, and MD5 hash processor written in System Verilog.

Language:SystemVerilogStargazers:3Issues:1Issues:0
Language:VerilogLicense:GPL-3.0Stargazers:1Issues:0Issues:0
Language:JavaStargazers:1Issues:0Issues:0
Language:C++Stargazers:1Issues:0Issues:0
Language:SystemVerilogLicense:GPL-3.0Stargazers:1Issues:1Issues:0
Language:CStargazers:1Issues:0Issues:0
Language:SystemVerilogLicense:GPL-3.0Stargazers:1Issues:1Issues:0
Language:SystemVerilogStargazers:1Issues:1Issues:0
Language:PythonStargazers:0Issues:0Issues:0
Language:JavaScriptStargazers:0Issues:1Issues:0
Language:CStargazers:0Issues:1Issues:0