Kathan's repositories
CRC_parallel
Python scripts to generate verilog design and testbench for CRC bits in combinational logic.
Language:C000
a_dot_i
Machine Learning, Deep Learning algorithms
000
Language:Python000
cs20si
Stanford University: CS 20: Tensorflow for Deep Learning Research
Language:Python000
fullcustom-microprocesssor
Highlights of "Full-custom design of General Purpose Microprocessor"
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Layout_Router
Synthesizable design of layout router of 3-D maze for two paths using Lees Algorithm with modifications to increase run time efficiency
Language:Verilog000
os_proj
OS projects
Language:C000
whats_the_time
Flutter app to fetch real time for different preset locations.
Language:Dart000