zzm432

zzm432

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zzm432's repositories

PicBed

PicBed Repo!

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MPSoC-DMA

Direct Access Memory for MPSoC

License:MITStargazers:0Issues:0Issues:0

axi_dma

General Purpose AXI Direct Memory Access

License:MITStargazers:0Issues:0Issues:0

axi-dma-controller

AXI4-based Direct Memory Access (DMA) controller

License:MITStargazers:0Issues:0Issues:0

MS_DMAC_AHBL

A Direct Memory Access Controller (DMAC) with AHB-lite bus interface

License:Apache-2.0Stargazers:0Issues:0Issues:0

automatic-verilog

automatic-verilog based on vimscript

License:GPL-3.0Stargazers:0Issues:0Issues:0

SM9_FREE

基于Miracl的国密算法SM9实现

License:BSD-2-ClauseStargazers:0Issues:0Issues:0
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micro-ecc

ECDH and ECDSA for 8-bit, 32-bit, and 64-bit processors.

License:BSD-2-ClauseStargazers:0Issues:0Issues:0

scared

Make your first side-channel attack on public datasets with eShard. This is a mirror of scared Gitlab repository. All contributions and merge request must be done through Gitlab project.

License:AGPL-3.0Stargazers:0Issues:0Issues:0

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

License:NOASSERTIONStargazers:0Issues:0Issues:0

fio

Flexible I/O Tester

License:GPL-2.0Stargazers:0Issues:0Issues:0

side-channel-analysis-toolbox

This is a project in which side-channel attacks are researched and developed.

License:MITStargazers:0Issues:0Issues:0

wujian100_open

IC design and development should be faster,simpler and more reliable

License:MITStargazers:0Issues:0Issues:0

mdma

AXI Mini Direct Memory Access (verilog)

License:MITStargazers:0Issues:0Issues:0
License:MITStargazers:0Issues:0Issues:0

pysm4

Python SM4

License:MITStargazers:0Issues:0Issues:0

Hello-world

First project

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nano-ecc

A very small ECC implementation for 8-bit microcontrollers

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