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ZiaZhang / gcd

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gcd

folders

  • rtl
  • sim
  • syn
  • fpga

branchs

- master brach

- direct

- 4 stage parellel

- clock gating(tbd)

About

Languages

Language:Tcl 95.6%Language:Verilog 3.4%Language:Perl 0.8%Language:Makefile 0.1%Language:Shell 0.1%