z1255's repositories
rsd
RSD: RISC-V Out-of-Order Superscalar Processor
Team5-OOO-RISCV-core
Senior Design project building a simple, out-of-order, RISC-V core:
tiny-gpu
A minimal GPU design in Verilog to learn how GPUs work from the ground up
NyuziProcessor
GPGPU microprocessor architecture
riscv-dv
Random instruction generator for RISC-V processor verification
vivado-on-silicon-mac
Installs Vivado on M1/M2 macs
memory_verification_using_system_verilog
In this respiratory having two verification methods first have without scoreboard and monitor and second with includes all component
e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
FPU_new
For CPU experiment
Cache-Controller
Two Level Cache Controller implementation in Verilog HDL
riscy-OOO
RiscyOO: RISC-V Out-of-Order Processor
seucourseshare
东南大学课程共享计划
CNRV-FPU
Basic floating-point components for RISC-V processors
OpenMIPS
A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance
Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
ECE745_ASICVerification
Final Testbench for LC3 Microcontroller
ridecore
RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
ECE745_LC3_Verification
North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog
uart16550
UART 16550 core