Yym996's repositories
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
pulpissimo
This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.
tinyriscv
A very simple and easy to understand RISC-V core.
riscv
RISC-V CPU Core (RV32IM)
lecture-examples
Sample scripts used in the lectures of the CEL (Communications Engineering Lab) at KIT
tiny
MLPerf™ Tiny is an ML benchmark suite for extremely low-power systems such as microcontrollers
riscv-binutils-gdb
RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
CNN-On-FPGA
FPGA
RISC-V-1
Repository for Hornet RISC-V Core
FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
tiny-dnn
header only, dependency-free deep learning framework in C++14
riscv-soc-book
关于RISC-V你所需要知道的一切
LSTMAssignment-DLNN2020
LSTM Character-based language Model for the DLNN Course Summer 2020
RISC-V
A simple RISC-V CPU written in Verilog.
CNN_C_forword
使用c语言完成Lenet-5的前向传播过程
CNN-use-C-achieve
LeNet-5 use c achieve
Cpp-0-1-Resource
C++ 匠心之作 从0到1入门资料
TensorFlow-Convolutional-AutoEncoder
This is an implementation of Convolutional AutoEncoder using only TensorFlow
PYNQ-project
PYNQ, Neural network Language model, Overlay