Yvan Tortorella's repositories
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
Language:SystemVerilogNOASSERTION000
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:C++NOASSERTION000
fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Language:SystemVerilogNOASSERTION000
hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
Language:SystemVerilogNOASSERTION000
NOASSERTION000
ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
Apache-2.0000
snitch
Lean but mean RISC-V system!
Apache-2.0000
Spoon-Knife
This repo is for demonstration purposes only.
000
Language:SystemVerilog000