Zihui Guo's repositories
awesome-directed-fuzzing
A curated list of awesome directed fuzzing research papers
000
cascade-artifacts
Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)
Language:Scala000
Language:PythonNOASSERTION000
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:AssemblyNOASSERTION000
cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Language:SystemVerilogApache-2.0000
Language:VerilogBSD-3-Clause000
fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
Language:SystemVerilogNOASSERTION000
GenFuzz
GPU-enabled Hardware Fuzzer using Genetic Algorithm
Language:C++000
NutShell
RISC-V SoC designed by students in UCAS
Language:ScalaNOASSERTION000
riscv-isa-manual
RISC-V Instruction Set Manual
Language:TeXCC-BY-4.0000
riscv-isa-sim
Spike, a RISC-V ISA Simulator
Language:CNOASSERTION000
rocket-chip
Rocket Chip Generator
Language:ScalaNOASSERTION000
simulator-independent-coverage
Project Repo for the Simulator Independent Coverage Research
Language:C++000
Language:C000
XiangShan
Open-source high-performance RISC-V processor
Language:ScalaNOASSERTION000