Y-BoBo's repositories
32-Verilog-Mini-Projects
Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM
basic_verilog
Must-have verilog systemverilog modules
bin2coe
Binary data to Xilinx COE BRAM Converter
CampusShame
互联网仍有记忆！那些曾经在校招过程中毁过口头offer、意向书、三方的公司！纵然人微言轻，也想尽绵薄之力！
carrv.github.io
Workshop on Computer Architecture Research with RISC-V (CARRV)
clash_for_windows_pkg
A Windows/macOS GUI based on Clash
cores-verilog
Various HDL (Verilog) IP Cores
CuAssembler
An unofficial cuda assembler, for all generations of SASS, hopefully ：）
CuPBoP
A framework that support executing unmodified CUDA source code on non-NVIDIA devices.
DeepLearningSystem
Deep Learning System core principles introduction.
gpgpu-sim_distribution
GPGPU-Sim provides a detailed simulation model of contemporary NVIDIA GPUs running CUDA and/or OpenCL workloads. It includes support for features such as TensorCores and CUDA Dynamic Parallelism as well as a performance visualization tool, AerialVisoin, and an integrated energy model, GPUWattch.
nudtpaper-yb_unused_2022
A LaTeX template for Master/PhD Thesis of NUDT
NVPTX-SPIRV-Translator
The translator that supports translating NVPTX to SPIR-V. This translator is modified from LLVM-SPIR-V Translator.
openc906
OpenXuantie - OpenC906 Core
openc910
OpenXuantie - OpenC910 Core
opene902
OpenXuantie - OpenE902 Core
opene906
OpenXuantie - OpenE906 Core
openpiton
The OpenPiton Platform
pdfs
Technically-oriented PDF Collection (Papers, Specs, Decks, Manuals, etc)
pocl
a clone of POCL that includes RISC-V newlib devices support and Vortex
pocl-initial
pocl - Portable Computing Language
ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
warp-v
WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.
zheda_jiaocai_pdf
浙江大学课程攻略共享计划