A more concise solution to "072_Bcdadd4"

[Lysias.]

The first bcd_fadder instance may be merged into the for loop as by tuning the genvar i and a larger temp signal c.

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );
    
    wire [4:0] c;
    
    assign c[0] = cin;
    assign cout = c[4];
    generate
        genvar i;
        for (i = 0; i < 4; i = i + 1) begin : adders
            bcd_fadd the_bcd_fadders ( 
                .a(a[i*4+3 : i*4]), 
                .b(b[i*4+3 : i*4]), 
                .cin(c[i]), 
                .cout(c[i+1]), 
                .sum(sum[i*4+3 : i*4]) 
            );
        end
    endgenerate

endmodule

file location:
https://github.com/xiaop1/Verilog-Practice/blob/master/2_Circuits/072_Bcdadd4.v

[xiaopi]

It works and is really concise, and i update the file by using your solution as a second choice. Thx~