xiaop1 / Verilog-Practice

HDLBits website practices & solutions

Geek Repo:Geek Repo

Github PK Tool:Github PK Tool

Adder100i

M-HHH opened this issue · comments

commented

//提供一个不一样的思路,两个always并行

module top_module( 
    input [99:0] a, b,
    input cin,
    output [99:0] cout,
    output [99:0] sum );
    
    assign cout[0] = a[0] & b[0] | a[0] & cin | b[0] & cin;
    assign sum[0]  = a[0] ^ b[0] ^ cin;
    
    integer i, j;
    
    always @ (*)
        begin
            for (i=1; i<100; i++)    
                begin
                    sum[i]  = a[i] ^ b[i] ^ cout[i-1];
                end
        end
    
    always @ (*)
        begin
            for(i=1; i<100; i++)
                begin
                    cout[i] = a[i] & b[i] | a[i] & cout[i-1] | b[i] & cout[i-1];  
                end
        end


endmodule

好思路,的确更加精简。我加到里面了~