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Library of VHDL components that are useful in larger designs.

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SDRAM DualPort generates bogus done signal on port switch after write

wrtlprnft opened this issue · comments

The DualPort module sometimes forwards the SdramCntl's done signal to the wrong port. This happens if pipelining is enabled and there is a write command on one port, followed immediately by a port switch and a command on the other port.

This is illustrated in the following signal trace: done1_o gets asserted in response to a write request on port 0, because in the DualPort module's eyes, the port switch has already occured at that point.

xess_bug

I don't know if there's a better solution, but I think I solved the problem by having DualPort generate the signals “from scrach” instead of forwarding them: 9562c33

On 08/28/2014 2:24 PM, wrtlprnft wrote:

The DualPort module sometimes forwards the SdramCntl's done signal to
the wrong port. This happens if pipelining is enabled and there is a
write command on one port, followed immediately by a port switch and a
command on the other port.

This is illustrated in the following signal trace: done1_o gets
asserted in response to a write request on port 0, because in the
DualPort module's eyes, the port switch has already occured at that point.

xess_bug
https://cloud.githubusercontent.com/assets/2631947/4080552/b42e57ea-2edf-11e4-89e1-01d894a52623.png

I don't know if there's a better solution, but I think I solved the
problem by having DualPort generate the signals “from scrach” instead
of forwarding them: 9562c33
9562c33


Reply to this email directly or view it on GitHub
#1.

Thanks for the bug report and solution! I'll take a look at it.


Dave Vandenbout / XESS Corp.
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