spi at t113-s3/D1s

[Genadi V. Zawidowski]

I propose two changes:

1. slow SPI speed (50 MHz too fast sometimes).
2. Add wait for clear start transfer bit before FIFO level check (required in user manual).
   

[jiang jianjun]

50MHZ clock is no problem at all for spi nor flash

[jiang jianjun]

wait for clear start transfer bit before FIFO level check。

This is unnecessary, because there is waiting for the fifo to have enough remaining space, and then write to the fifo.

[Genadi V. Zawidowski]

If transfer chunk size not equal to FIFO size, I got some problems if skipped transfer bit waiting.