spi at t113-s3/D1s
ua1arn opened this issue · comments
Genadi V. Zawidowski commented
jiang jianjun commented
50MHZ clock is no problem at all for spi nor flash
jiang jianjun commented
wait for clear start transfer bit before FIFO level check。
This is unnecessary, because there is waiting for the fifo to have enough remaining space, and then write to the fifo.
Genadi V. Zawidowski commented
If transfer chunk size not equal to FIFO size, I got some problems if skipped transfer bit waiting.