Wilson Xue's repositories
File-batch-renaming-script
Designed by Qitian_Fan
awesome-dv
Awesome ASIC design verification
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chatgpt-chinese-prompt-hack
利用prompt hack绕开OpenAI的内容政策限制
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crc-verilog-code-generator
A script that generates crc checksums for verilog code
Language:Python000
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e203_hbirdv2
The Ultra-Low Power RISC-V Core
Language:VerilogApache-2.0000
Language:C000
FPGATechnologyGroup
FPGA Technology Exchange Group相关文件管理
Language:VHDL000
gplgpu
GPL v3 2D/3D graphics engine in verilog
Language:VHDLGPL-3.0000
music-visualization
music visualization based on matlab
Language:MATLAB000
Language:Lua000
Language:Makefile000
Language:Makefile000
My_Vim_Settings
my vim settings
Language:Vim Script000
pynqz2-sd-hdmi
A simple hdmi output sample for pynq-z2
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BSD-3-Clause000
Real-time-music-visualization-system-based-on-PYNQ-Z2
Real-time music visualization system based on PYNQ-Z2
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simpleserial-ascon
Masked Ascon Software Implementations
CC0-1.0000
so-vits-svc
SoftVC VITS Singing Voice Conversion
AGPL-3.0000
SystemVerilog_Course
This is a detailed SystemVerilog course
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