Zhangqi Xu's repositories
2dconv-FPGA
A 2D convolution hardware implementation written in Verilog
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
axi_mem_if
Simple single-port AXI memory interface
cheat
cheat allows you to create and view interactive cheatsheets on the command-line. It was designed to help remind *nix system administrators of options for commands that they use frequently, but not frequently enough to remember.
cheatsheets
Community-sourced cheatsheets
CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
cnn_hardware_acclerator_for_fpga
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
convolution_network_on_FPGA
CNN acceleration on virtex-7 FPGA with verilog HDL
Deep-Neural-Network-Hardware-Accelerator
SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
doxygen-verilog
Doxygen with verilog support
fpga-hash-table
Simple hash table on Verilog (SystemVerilog)
FPGADesignElements
A self-contained online book containing a library of FPGA design modules and related coding/design guides.
fpu
synthesiseable ieee 754 floating point library in verilog
hdl
HDL libraries and projects
hdl_library
A library of verilog and vhdl modules
logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
memory
Generic memory implementations
neural-hardware
Verilog library for implementing neural networks.
Octavo
Verilog FPGA Parts Library. Old Octavo soft-CPU project.
oh
Verilog library for ASIC and FPGA designers
sock.sv
A simple TCP socket library for system verilog. Using the system verilog DPI, allows the user to read / write lines from a TCP socket connection.
SV-for-Design
Systemverilog Design Packages
SystemVerilogSHA256
SHA256 in (System-) Verilog / Open Source FPGA Miner
verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
verilog-buildingblocks
Library of generic verilog buildingblocks
Vitis_Libraries
Vitis Libraries