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2110363 Hardware Synthesis Lab I Files
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Language:Verilog 46.3%Language:Tcl 19.9%Language:JavaScript 10.7%Language:SystemVerilog 10.4%Language:Shell 6.1%Language:C 4.1%Language:Batchfile 1.1%Language:HTML 0.6%Language:VHDL 0.3%Language:Pascal 0.2%Language:Stata 0.1%Language:Python 0.1%Language:PureBasic 0.0%Language:Makefile 0.0%