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verilog-to-routing / vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

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[CI] Nightly Test Failures

AlexandreSinger opened this issue · comments

commented

The last 5 scheduled nightly CI Test runs have failed due to QoR failures. I think some of the golden values are incorrect:
Screenshot from 2024-07-02 14-54-17

vtr_reg_nightly_test1_odin:
Screenshot from 2024-07-02 14-50-04

vtr_reg_nightly_test2_odin:
Screenshot from 2024-07-02 14-51-52

vtr_reg_nightly_test3_odin:
Screenshot from 2024-07-02 14-52-39

I think these three golden ranges just need to be adjusted.

commented

@vaughnbetz Should we be concerned about these unexpected changes? Since these are not runtime issues these are things like negative slack and min_chan_width.

commented

No, I'm not very worried about them. Very small designs, just outside the QoR guardbands. Mostly Odin-II, which is also less important now. I agree; I think somehow we didn't get the right golden values. If you have the energy for it please go ahead and check in new golden results to fix them.