This repository contains code written as part of the final year undergraduate project titled "Exploring Resource-Performance Tradeoffs In Golden Gate". There are two subprojects contained within this repository -
(1) Chisel3-RV32I-CPU: HDL and simulation code for a 32-bit processor using the RV32I instruction set
(2) firesim-cam-files: Source code for compilation and software simulation of content addressable memories (CAMs) in FireSim's decoupled FPGA simulation environment
Instructions to run these can be found in the respective repositories.