varriola

pysc2

StarCraft II Learning Environment

EffectiveTensorflow

TensorFlow tutorials and best practices.

riscv-toolchain

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

ri5cy_gnu_toolchain

pulpino

An open-source microcontroller system based on RISC-V

rocket-chip

Rocket Chip Generator

zipcpu

A small, light weight, RISC CPU soft core

riscv-sodor

educational microarchitectures for risc-v isa

librecores-python

LibreCores Python library

librecores-pipeline-lib

Jenkins Pipeline library for LibreCores CI

lcci-python

LibreCores CI Python library

gsoc-museum-edsac

GSoC 2017: Museum on FPGA - EDSAC

docker-images

CI Docker Images

librecores-backend

Backend Infrastructure of LibreCores (mostly docs)

docker-tools

Just a set of Dockerfiles and tools for FuseSoC

librecores-web

LibreCores Web Site

librecores-ci-jenkins-server

LibreCores Continuous Integration

autofpga

A utility for Composing FPGA designs from Peripherals

AtomFpga

Dave's version of the Acorn Atom FPGA, based on AlanD's original from stardot.org.uk

pybind11

Seamless operability between C++11 and Python

mipsfpga-plus

MIPSfpga+ allows loading programs via UART and has a switchable clock

schoolMIPS

CPU microarchitecture, step by step

Sol-R

Open-Source CUDA/OpenCL Speed Of Light Ray-tracer

pywonderland

A tour in the wonderland of math with python.

riscv-formal

RISC-V Formal Verification Framework

sby

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

picorv32

PicoRV32 - A Size-Optimized RISC-V CPU