Vardhan Suroshi's repositories
Memory-Design-And-Testing
The project involves the design of a 4X4 (16-bit) SRAM Memory Array using Cadence Virtuoso
VLSI-ASIC-Design-Flow
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
SCL-Design-Workshop-24
Welcome to the Standard Cell Design Workshop repository. Here, you'll find all the necessary files and resources for a hands-on learning experience.
VLSI-Physical-Design-Flow
This project offers an immersive tutorial experienced within the context of the Advanced Physical Design, focusing on the utilization of OpenLANE. This repo is the continuity of VLSI ASIC Design Flow
Vedic-Multiplier-From-RTL2GDS
GitHub repository dedicated to VLSI ASIC Design using open-source tools! A simple Vedic Multiplier is Forged, through the entire RTL to GDS process that meets various PPA
eUVM_worskshop_avst_adder
Example setup for UVM driven Icarus Verilog Simulation
VardhanSuroshi
Config files for my GitHub profile.