ucam-comparch / clarvi

Clarvi simple RISC-V processor for teaching

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Machine mode version 1.7

PeterRugg opened this issue · comments

The riscv privileged mode spec. has changed in later versions, including changing CSR addresses, which causes the current rv32mi tests to fail.

riscv-tests fails due to mtvec (from v1.7) being aliased to misa (from v1.9 and later):
riscv-software-src/riscv-tests#32