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A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform Machine Learning models i.e. MLP Neural Networks on an FPGA using C, C++, Hardware Description Languages (HDL), High Level Synthesis (HLS) and Verilog.
UART modules interface using Verilog for the Basys3 board (Digilent). Computer Architecture 2023. FCEFyN, UNC, Argentina