floating-point-alternative

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/ Posit-arithmetic-unit
This repository provides a parameterized hardware implementation of a Posit Arithmetic Unit (PAU) written in Verilog. It supports addition, subtraction, multiplication, and division over configurable posit formats, and includes a full verification framework using a C++ golden reference model.
fpga hardware-accelerator hardware-design hdl posit posit-arithmetic rtl systemverilog verilog floating-point-alternative machine-learning-accelerator universal-number
Language:Verilog

/ Posit-arithmetic-unit