这是武汉大学计算机弘毅班开设的“计算机组成与设计”专业课对应的实验部分。此仓库保存了本人独立完成的实验源码。 计组实验跨越了两个学期。大二上完成了的在Modelsim上编写、仿真、测试的任务有：
- 单周期CPU（文件夹为./Single Cycle Processor)
- 多周期CPU（文件夹为./Multicycle Processor)
- 流水线CPU [五级流水线，支持Forwarding，Hazard detection] （文件夹为./Pipeline Processor)
（注：每个文件夹下均有一个work文件夹，创建项目时由Modelsim自动生成。为了使仓库轻量，work文件夹均未跟踪。读者需自己创建项目，把源码复制到项目中即可）
大二下完成了“下板子”工作，将代码下载到FPGA板子中（SOC：system on chip)。为了能在板子上运转，在上学期的项目的基础上进行了删改：更改了端口的名称（为了与板子现有模块匹配）、删减了部分模块（eg.Memory为外置模块，不需要CPU提供）。具体的工作有：
- 单周期CPU（文件夹为./SCPU_experiment)
- 多周期CPU（文件夹为./MCPU_experiment)
- 流水线CPU [五级流水线，支持Forwarding，Hazard detection] （文件夹为./PCPU_experiment)
- 流水线CPU基础上的中断(INT)、异常实现(syscall)实现 [五级流水线，支持Forwarding，Hazard detection]（文件夹为./PCPU_INT)
（注1：先在Modelsim上仿真，没问题后再在实物上操作）
（注2：中断异常实验要求自己写测试文件.asm，最终也没有做完，投入了大量的时间和精力，但是实在找不到bug在哪里/(ㄒoㄒ)/~~跑不出应有的效果，已尽力，只能放下啦……）
祝好！
English version
This is the experimental part of the "Computer Organization and Design" course offered by Hongyi class of Wuhan University. This repository holds the source codes written by me independently. The experiment spans two semesters. The tasks that have been written, simulated, and tested on Modelsim, which were completed on the first semester of sophomore, are:
- Single-cycle CPU (the folder is ./Single Cycle Processor)
- Multi-cycle CPU (the folder is ./Multicycle Processor)
- Pipeline CPU [Five-stage pipeline, support for Forwarding, Hazard detection] (the folder is ./Pipeline Processor)
(Note: There is a 'work' folder under each folder. It is automatically generated by Modelsim when creating the project. In order to make the repository lightweight, the work folder is not tracked. Readers need to create a project and copy the source codes into the project. )
On the second semester of sophomore, the codes were downloaded to the FPGA board (SOC: system on chip). In order to run on the board, the project was slightly modified: the name of some ports were changed (in order to match the existing modules of the board), and some modules were deleted (eg.Memory is an external module, no need to provide by CPU). The specific work is:
- Single-cycle CPU (the folder is ./SCPU_experiment)
- Multi-cycle CPU (the folder is ./MCPU_experiment)
- Pipeline CPU [Five-stage pipeline, support for Forwarding, Hazard detection] (the folder is ./PCPU_experiment)
- Pipeline CPU based interrupt (INT), exception(syscall) implementation [Five-stage pipeline, support Forwarding, Hazard detection] (the folder is ./PCPU_INT)
(Note 1: First operate on Modelsim. If there is no problem with the simulation, turn to the physical object.)
(Note 2: The experiment of INT & syscall requires to write the test file .asm on your own. Unluckily, I failed to finish it at the end. A lot of time and effort were put into it, but still I couldn't find the bug /(ㄒoㄒ)/~~ The desired result didn't achieved. The last and the only thing I could do is let it go...)
good luck!
by Tina