TCal's repositories
fomu-workshop
Support files for participating in a Fomu workshop
litex-boards
LiteX boards files
symbiflow-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
symbiflow-examples
Examples designs for showing different ways to use SymbiFlow toolchains.
verilator-make-env-test
Demonstration of issue with Verilator package in the Conda environment.
bazel_rules_hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
CFU
RISC-V FPGA SIG Custom Function Unit Specification
containers
Building and deploying container images for open source electronic design automation (EDA)
icebreaker-examples
This repository contains small example designs that can be used with the open source icestorm flow.
icebreaker-nmigen-examples
This repository contains icebreaker examples for nmigen, a refresh of migen.
klayout
KLayout Main Sources
litespi
Small footprint and configurable SPI core
litex
Build your hardware, easily!
litex-buildenv
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
nextpnr
nextpnr portable FPGA place and route tool
nmigen-tutorial
A tutorial for using nmigen
prjxray
Documenting the Xilinx 7-series bit-stream format.
pythondata-cpu-vexriscv
Python module containing verilog files for vexriscv cpu (for use with LiteX).
symbiflow-docs
Documentation for SymbiFlow
tcal-x.github.io
The blog of tcal-x
tcal-yosys-vivado
Examples using Yosys-Vivado flow
xls
XLS: Accelerated HW Synthesis
yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.