syedimaduddin / msvsd4bituc

VSD Mixed-signal PD Research Program

VSD Mixed-signal PD Research Program

This repository contains information about a 10-week program that uses SKY130 PDK and open-source flow tools to tape out chips.

Each week, participants must perform tasks and meet requirements to stay in the program.

My weekly tasks and simulations are compiled in a directory for each week.

Below is a summary of my activities each week

Week-1

1. Tools installed
   • Magic
   • Xschem
   • Ngspice
   • Netgen
   • ALIGN
2. Pre-layout simulation for an inverter
   • Inverter schematic in Xschem
   • Making symbol
   • Test and simulate the inverter
3. Post-layout simulation for an inverter
   • Layout implementation
   • Run LVS with using netgen
   • Post-layout simulation
   • Generating layout with using Align

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Week-2

1. Post-layout simulation for Inverter by using Align
2. Pre-layout simulation of FN
   • Schematic implementation
   • Test and simulation
   • Calculation of the delay
3. Post-layout simulation of FN
   • Layout implementation with Align
   • Extracting parasitic capicitances using magic
   • Post-layout simulation
   • comparison between pre-layout and post-layout

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Week-3

1. OpenFASoC installation
   • Openroad installation
   • Yosys installation
   • Klayout installation
   • OpenFASoC installation
2. Running a sample using OpenFASoC
   • Circuit structure
   • Verilog generation
   • Synthesis

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Week-4

1. Basics of ring oscillator
2. Pre-layout simulation of a ring oscillator
   • Schematic implementation
   • Test and simulation
   • calculation of the period
3. Post-layout simulation of a ring oscillator
   • Layout implementation with Align
   • Extracting parasitic capicitances using magic
   • Post-layout simulation
4. comparison between pre-layout and post-layout

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Week-5

1. Basics of Analog to Digital Converter
2. 1-Bit ADC
3. Pre-Layout Simulation of a 1-Bit ADC
   • Schematic implementation
   • calculation of the period
4. Post-Layout Simulation of a 1-Bit ADC
   • Layout implementation with Align
   • Extracting parasitic capicitances using magic
   • Post-layout simulation
5. Comparison Between Post-Layout and Pre-Layout Results of ADC
6. Pre-Layout simulation of combination of RO and ADC(RO_ADC)
7. Post-Layout simulation of RO_ADC
8. Comparison of Pre and Post-Layout results of RO_ADC
9. Top Module of Verilog Code for RO and ADC

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Week-6

1. Layout implementation for Ring Oscillator and ADC using OpenFASoC

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Week-7

1. Reduce the area of the Macro in OpenFASoC
2. Connect the VDD and VSS to the Macro

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