suyashmahar

RISC-processor

Simple single cycle RISC processor written in Verilog

Clipboarder

Feature packed clipboard manager for Windows

pine

:evergreen_tree: Hassle free .gitignore manager

europa

🌕 JupyterLab's Desktop client

ecn104-assignments

Assignment repository for teaching Verilog as part of ECN-104, spring 2018,19

fsed

:scissors: Real time editing of files opened in a process; sed for files

resume

Template for my CV+Resume

ndn-fib

Verilog description and analysis for FPGA based Longest Prefix Matching for Forwarding Information Base in NDN routers.

urisc

Single instruction processor and toolchain

jekyll-conf-website

Simple conference website jekyll template

ramulator-wolfram

WoLFRaM implementation using ramulator

use-package.sh

:package: A better way to manage your shell's .rc file

3-2-os

argparse-manpage

Automatically build man-pages for your Python project

chocopy-wasm-compiler

GolangTutorial

A small repo so we can all syncronize during the tutorial

libivy

Distributed shared memory using IVY central manager model.

libpaper

linux-2.6.33

llvm-hs

Haskell bindings for LLVM

org-outer-indent

An outer indentation org mode

personal-website

pmdk

Persistent Memory Development Kit

py-wasm

Compile python to webassembly

ramulator

A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

simpoint-patched

Patched for compilation issues. Tested with c++ (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0

sys

Sys: A Static/Symbolic Tool for Finding Good Bugs in Good (Browser) Code

TRF

Tandem Repeats Finder: a program to analyze DNA sequences

up_sources_stable

Stable sources for use-package.sh

VAMPIRE

An open-source DRAM power model based on extensive experimental characterization.