苏健's repositories

Xilinx-FPGA-PCIe-XDMA-Tutorial

Xilinx FPGA PCIe 保姆级教程 ——基于 PCIe XDMA IP核

Language:BatchfileStargazers:1Issues:0Issues:0

ZYNQ-NVDLA

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Language:VerilogStargazers:1Issues:1Issues:0

almond

A Scala kernel for Jupyter

Language:ScalaLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0
Language:VerilogStargazers:0Issues:0Issues:0

Bedrock

LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:0Issues:0

biriscv

32-bit Superscalar RISC-V CPU

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

ChatGPT-Paper-Reader

This repo offers a simple interface that helps you to read&summerize research papers in pdf format. You can ask some questions after reading. This interface is developed based on openai API and using GPT-3.5-turbo model.

Language:PythonStargazers:0Issues:0Issues:0

core_mmc

MMC (and derivative standards) host controller

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

dma_ip_drivers

Xilinx QDMA IP Drivers

Language:CStargazers:0Issues:0Issues:0
Language:VerilogStargazers:0Issues:1Issues:0

gpt4-pdf-chatbot-langchain

GPT4 & LangChain Chatbot for large PDF docs

Language:TypeScriptStargazers:0Issues:0Issues:0

hdl

HDL libraries and projects

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:0Issues:0

iob-mem

Verilog behavioral description of various memories

Language:VerilogLicense:MITStargazers:0Issues:1Issues:0

no-OS

Software drivers in C for systems without an operating system

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0

pp4fpgas-cn

中文版 Parallel Programming for FPGAs

Language:CSSStargazers:0Issues:1Issues:0

Spinal-bootcamp

SpinalHDL-tutorial based on Jupyter Notebook

Language:Jupyter NotebookStargazers:0Issues:1Issues:0

SpinalHDL

Scala based HDL

Language:ScalaLicense:NOASSERTIONStargazers:0Issues:1Issues:0

SpinalTemplateSbt

A basic SpinalHDL project

Language:ScalaStargazers:0Issues:1Issues:0

UART-RS232

RS232 Receiver/Transmitter Verilog for FPGA

Language:VerilogStargazers:0Issues:1Issues:0

verilog-can

Verilog CAN controller that is compatible to the SJA 1000.

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:1Issues:0
Stargazers:0Issues:0Issues:0

srio_test

Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)

License:MITStargazers:0Issues:0Issues:0

tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

License:Apache-2.0Stargazers:0Issues:0Issues:0